For more than half a century, the cathode ray tube (CRT) has been the principal electronic device for displaying visual information. The widespread usage of the CRT may be ascribed to the remarkable quality of its display characteristics in the realms of color, brightness, contrast and resolution. One major feature of the CRT permitting these qualities to be realized is the use of a luminescent phosphor coating on a transparent faceplate.
Conventional CRT's, however, have the disadvantage that they require significant physical depth, i.e., space behind the actual display surface, making them bulky and cumbersome. They are fragile and, due in part to their large vacuum volume, can be dangerous if broken. Furthermore, these devices consume significant amounts of power.
The advent of portable computers has created intense demand for displays which are light-weight, compact and power efficient. Since the space available for the display function of these devices precludes the use of a conventional CRT, there has been significant interest in efforts to provide satisfactory flat panel displays having comparable or even superior display characteristics, e.g., brightness, resolution, versatility in display, power consumption, etc. These efforts, while producing flat panel displays that are useful for some applications, have not produced a display that can compare to a conventional CRT.
Currently, liquid crystal displays are used almost universally for laptop and notebook computers. In comparison to a CRT, these displays provide poor contrast, only a limited range of viewing angles is possible, and, in color versions, they consume power at rates which are incompatible with extended battery operation. In addition, color screens tend to be far more costly than CRT's of equal screen size.
As a result of the drawbacks of liquid crystal display technology, thin film field emission display technology has been receiving increasing attention by industry. Flat panel displays utilizing such technology employ a matrix-addressable array of pointed, thin-film, cold field emission cathodes in combination with an anode comprising a phosphor-luminescent screen.
The phenomenon of field emission was discovered in the 1950's, and extensive research by many individuals, such as Charles A. Spindt of SRI International, has improved the technology to the extent that its prospects for use in the manufacture of inexpensive, low-power, high-resolution, high-contrast, full-color flat displays appear to be promising.
Advances in field emission display technology are disclosed in U.S. Pat. No. 3,755,704, "Field Emission Cathode Structures and Devices Utilizing Such Structures," issued 28 Aug. 1973, to C. A. Spindt et al.; U.S. Pat. No. 4,940,916, "Electron Source with Micropoint Emissive Cathodes and Display Means by Cathodoluminescence Excited by Field Emission Using Said Source," issued 10 Jul. 1990 to Michel Borel et al.; U.S. Pat. No. 5,194,780, "Electron Source with Microtip Emissive Cathodes," issued 16 Mar. 1993 to Robert Meyer; and U.S. Pat. No. 5,225,820, "Microtip Trichromatic Fluorescent Screen," issued 6 Jul. 1993, to Jean-FredeClerc. These patents are incorporated by reference into the present application.
The Clerc ('820) patent discloses a field emission flat panel display having a glass substrate on which are arranged a matrix of conductors. In one direction of the matrix, conductive columns comprising the cathode electrode support the microtips. In the other direction, above the column conductors, are perforated conductive rows comprising the gate electrode. The row and column conductors are separated by an insulating layer having holes permitting the passage of the microtips, each intersection of a row and column corresponding to a pixel. As stated in the Clerc patent, silica is commonly used as the insulating layer material.
One area for improvement of field emission displays of the current technology is in the material used as the insulating layer separating the cathode and gate electrodes. Since one of the main advantages of field emission displays is low power consumption, any reduction in power consumption further enhances this competitive advantage. The emitter portion of the display is responsible for the largest portion of power consumption by the display. The emitter power consumption is directly related to the dielectric constant (switching capacitance) of the insulating layer between the cathode and gate electrodes. This problem becomes more pronounced at smaller hole geometries because as the hole diameter decreases, the thickness of the dielectric layer must be reduced to maintain the tip aspect ratio. Thinning the dielectric layer increases the capacitance, if the dielectric constant remains the same.
Probably the most common semiconductor dielectric material is silicon dioxide, which has a relative dielectric constant of about 3.9. In contrast, air (including partial vacuum) has a relative dielectric constant of just over 1.0. Consequently, many capacitance reducing schemes have been devised to at least partially replace solid dielectrics with air by semiconductor and electronics manufacturers in designing various integrated circuits.
U.S. Pat. No. 4,987,101, issued to Kaanta et al., on Jan. 22, 1991, describes a method for fabricating gas (air) dielectrics which comprises depositing a temporary layer of removable material between supports (such as conductors), covering this with a capping insulator layer, opening access holes in the cap, extracting the removable material through these access holes, then closing the access holes. This method can be cumbersome, partially because it requires consideration of access hole locations in the design rules and alignment error budget during circuit design, as well as requiring extra processing steps to create and then plug the holes. This method may also create large void areas which have essentially no means of handling mechanical stress and heat dissipation.
U.S. Pat. No. 5,103,288, issued to Sakamoto, on Apr. 7, 1992, describes a multilayered wiring structure which decreases capacitance by employing a porous dielectric with 50% to 80% porosity (porosity is the percentage of a structure which is hollow) and pore sizes of roughly 5 nm to 50 nm. This structure is typically formed by depositing a mixture of an acidic oxide and a basic oxide, heat treating to precipitate the basic oxide, and then dissolving out the basic oxide. Dissolving all of the basic oxide out of such a structure may be problematic, because small pockets of the basic oxide may not be reached by the leaching agent. Furthermore, several of the elements described for use in the basic oxides (including sodium and lithium) are generally considered contaminants in the semiconductor industry, and as such are usually avoided in a production environment. Creating only extremely small pores (less than 10 nm) may be difficult using this method.
Another method of forming porous dielectric films on semiconductor substrates (the term "substrate" is used broadly herein to include any layers formed prior to the conductor/insulator level of interest) is described in U.S. Pat. No. 4,652,467, issued to Brinker et al., on Mar. 24, 1987. This patent teaches a sol-gel technique for depositing porous films with controlled porosity and pore size (diameter), wherein a solution is deposited on a substrate, gelled, and then cross-linked and densified by removing the solvent through evaporation, thereby leaving a porous dielectric. This method has as a primary objective the densification of the film, which teaches away from low dielectric constant application. Dielectrics formed by this method are typically 15% to 50% porous, with a permanent film thickness reduction of at least 20% during drying. The higher porosities (e.g. 40%-50%) can only be achieved at pore sizes which are generally too large for such microcircuit applications. These materials are usually referred to as xerogels, although the final structure is not a gel, but an open-pored (the pores are generally interconnected, rather than being isolated cells) porous structure of a solid material.
Today the material generally used as the gate dielectric in field emission display devices is silicon dioxide (SiO.sub.2) or doped SiO.sub.2 to control the stress. As the thickness of the gate dielectric for flat panel displays is reduced to accommodate smaller hole diameters, the capacitive coupling present with the use of the standard SiO.sub.2 gate dielectric increases and adversely affects proper device operation. The use of organic dielectrics such as polyimide and amorphous Teflon have been attempted, but they require keeping the processing temperature below 300.degree. C. Since current upper processing temperatures for flat panel displays is around 400.degree. C. to 450.degree. C. these organic dielectrics cannot be used. Furthermore, organic materials are subject to outgassing at the very low pressures, typically of the order of 10.sup.-7 torr, maintained in field emission flat panel display devices. Such outgassing increases the pressure within the device and degrades the performance of the emitters.
One way to diminish power consumption is to decrease the dielectric constant of the insulating gate dielectric. What is needed is a material which has a lower dielectric constant than SiO.sub.2. More ideally, what is needed is a low dielectric constant material that is vacuum compatible and able to withstand temperatures greater than 400.degree. C.